1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, more particularly to a method for fabricating metal oxide semiconductor (MOS) transistors, which can reduce the junction capacitance without a degradation of characteristics in a transistor even in gate line narrowing.
2. Description of the Prior Art
As generally known in the art, with the high-integration of semiconductor devices, the line narrowing of a gate electrode has been caused so that the length of a channel has been reduced, which generates a short channel effect by which threshold voltage of a transistor is rapidly reduced. Thus, various technologies have been proposed so as to reduce the short channel effect.
Herein, the prevention of the short channel effect is a problem to be solved for a high integration of a semiconductor device. One way to solve the problem is to form a lightly doped drain (LDD) region.
An MOS transistor of the prior art adapting LDD structure will be now described with reference to FIGS. 1A to 1C.
Referring to FIG. 1A, ion implantation processes for well formation, field stop formation, punch stop formation and threshold voltage adjustment are successively conducted to the whole area of a semiconductor substrate 1 having a trench type isolation layer 2. Then, a gate oxide layer 3a and a gate conductive layer 3b are successively formed, and the gate oxide layer 3a and the gate conductive layer 3b are patterned to form a gate electrode 4.
Referring to FIG. 1B, ion implantation of low concentration impurities is conducted to the semiconductor substrate 1 including the gate electrode 4 to form LDD regions 5 on both side portions of the gate electrode 4. Then, an oxide layer 6a and a nitride layer 6b are successively deposited on the semiconductor substrate 1 so as to cover the gate electrode 4.
Referring to FIG. 1C, the oxide layer 6a and the nitride layer 6b are blanket etched to form spacers 7 on both side walls of the gate electrode 4. Then, ion implantation of high concentration impurities is conducted to the whole area of the substrate, and an annealing treatment is conducted to former to form source/drain regions 8 with an LDD region 5 formed in the substrate on both side portions of the gate electrode 4.
However, in the fabricating method of MOS transistor of the prior art, ion implantation processes for well formation, field stop formation, punch stop formation and threshold voltage adjustment are successively conducted to the whole area of active region of the semiconductor substrate so as to reduce a shot channel effect, thus increasing dopants concentration of well in the source/drain regions.
In this case, the increase or the dopants concentration of well causes a generation of the junction capacitance in the source/drain region, and the junction capacitance causes a delay of gate signal, which functions to reduce reliability of the semiconductor device. Particularly, these are some of the problems to be solved in conjunction with the tendency of gradual increase of degradation of device characteristics due to a short channel effect according to a gradual reduction of critical dimensions of the gate electrode.